Merge branches 'clk-renesas', 'clk-socfpga', 'clk-amlogic' and 'clk-canaan' into clk-next

* clk-renesas: (36 commits)
  clk: renesas: r9a08g045: Drop unused pm_domain header file
  clk: renesas: r8a779g0: Add DSC clock
  clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowing
  clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macro
  clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones
  clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro
  clk: renesas: rzg2l: Simplify SAM PLL configuration macro
  clk: renesas: r8a73a4: Add ZT/ZTR trace clocks
  dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6
  clk: renesas: r9a08g046: Add RSPI clocks and resets
  clk: renesas: r9a08g046: Add SSIF-2 clocks and resets
  clk: renesas: r9a08g046: Add RSCI clocks and resets
  clk: renesas: cpg-mssr: Add number of clock cells check
  clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()
  clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()
  clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocks
  clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets
  clk: renesas: r9a09g047: Add support for DSI clocks and resets
  clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK
  clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks
  ...

* clk-socfpga:
  clk: socfpga: agilex: implement l3_main_free_clk

* clk-amlogic:
  dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock
  dt-bindings: clock: amlogic: Fix redundant hyphen in "amlogic,t7-gp1--pll" string.

* clk-canaan:
  clk: canaan: Add clock driver for Canaan K230
  dt-bindings: clock: Add Canaan K230 clock controller