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| author |   Mats Randgaard <matrandg@cisco.com> | 2013-08-14 09:26:28 -0300 |
|---|---|---|
| committer |   Mauro Carvalho Chehab <m.chehab@samsung.com> | 2013-08-24 04:25:42 -0300 |
| commit | f3b33ede51903e6cc211d9f0bdecc65646b71f17 (patch) | |
| tree | b9bbf6e353ff621fdb10706faf9590d737bf174e /include/media/v4l2-dv-timings.h | |
| parent | [media] adv7604: corrected edid crc-calculation (diff) | |
| download | wireguard-linux-f3b33ede51903e6cc211d9f0bdecc65646b71f17.tar.xz wireguard-linux-f3b33ede51903e6cc211d9f0bdecc65646b71f17.zip | |
[media] ad9389b: change initial register configuration in ad9389b_setup()
- register 0x17: CSC scaling factor was set to +/- 2.0. This register
is set by ad9389b_csc_conversion_mode() to the right value.
- register 0x3b: bits for pixel repetition and CSC was set to zero,
but that is the default value.
Signed-off-by: Mats Randgaard <matrandg@cisco.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Diffstat (limited to 'include/media/v4l2-dv-timings.h')
0 files changed, 0 insertions, 0 deletions