diff options
| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-10-15 20:26:10 +0100 |
|---|---|---|
| committer |   Biju Das <biju.das.jz@bp.renesas.com> | 2025-12-16 07:25:04 +0000 |
| commit | 99b98993ae010b86d0ec0d779c1c8be890057568 (patch) | |
| tree | b6ab1f4bd32507762c23c62ccc52a32f107e4f64 /include/rdma/ssh:/git@git.zx2c4.com/git: | |
| parent | dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and RZ/V2N (diff) | |
drm: renesas: rz-du: mipi_dsi: Add LPCLK clock support
Add LPCLK clock handling to the RZ/G2L MIPI DSI driver to support proper
DSI timing parameter configuration on RZ/V2H SoCs. While lpclk is present
on both RZ/G2L and RZ/V2H SoCs, the RZ/V2H SoC specifically uses the lpclk
rate to configure the DSI timing parameter ULPSEXIT.
Introduce a new lpclk field in the rzg2l_mipi_dsi structure and acquire
the "lpclk" clock during probe to enable lpclk rate-based timing
calculations on RZ/V2H while maintaining compatibility with RZ/G2L.
Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20251015192611.241920-7-prabhakar.mahadev-lad.rj@bp.renesas.com
Diffstat (limited to 'include/rdma/ssh:/git@git.zx2c4.com/git:')
0 files changed, 0 insertions, 0 deletions