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authorClaudiu Manoil <claudiu.manoil@nxp.com>2020-01-06 03:34:13 +0200
committerDavid S. Miller <davem@davemloft.net>2020-01-05 23:22:32 -0800
commit6517798dd3432a0002109809bf74e4fcf9bb0c7d (patch)
treecca490604c8189f518d43f74173a394d756eb6e4 /include/soc
parentnet: dsa: Pass pcs_poll flag from driver to PHYLINK (diff)
downloadwireguard-linux-6517798dd3432a0002109809bf74e4fcf9bb0c7d.tar.xz
wireguard-linux-6517798dd3432a0002109809bf74e4fcf9bb0c7d.zip
enetc: Make MDIO accessors more generic and export to include/linux/fsl
Within the LS1028A SoC, the register map for the ENETC MDIO controller is instantiated a few times: for the central (external) MDIO controller, for the internal bus of each standalone ENETC port, and for the internal bus of the Felix switch. Refactoring is needed to support multiple MDIO buses from multiple drivers. The enetc_hw structure is made an opaque type and a smaller enetc_mdio_priv is created. 'mdio_base' - MDIO registers base address - is being parameterized, to be able to work with different MDIO register bases. The ENETC MDIO bus operations are exported from the fsl-enetc-mdio kernel object, the same that registers the central MDIO controller (the dedicated PF). The ENETC main driver has been changed to select it, and use its exported helpers to further register its private MDIO bus. The DSA Felix driver will do the same. Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/soc')
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