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authorLu, Han <han.lu@intel.com>2015-12-07 15:59:13 +0800
committerTakashi Iwai <tiwai@suse.de>2015-12-07 09:04:44 +0100
commit7c23b7c1996597dd9d60bb282fb5fa1be6ebd18b (patch)
treec88af19892551e1e0c3bc8171ffcba1b15c7176f /include/sound/hda_register.h
parentALSA: rme96: Fix unexpected volume reset after rate changes (diff)
downloadwireguard-linux-7c23b7c1996597dd9d60bb282fb5fa1be6ebd18b.tar.xz
wireguard-linux-7c23b7c1996597dd9d60bb282fb5fa1be6ebd18b.zip
ALSA: hda - Fix playback noise with 24/32 bit sample size on BXT
In BXT-P A0, HD-Audio DMA requests is later than expected, and makes an audio stream sensitive to system latencies when 24/32 bits are playing. Adjusting threshold of DMA fifo to force the DMA request sooner to improve latency tolerance at the expense of power. v2: move Intel specific code to hda_intel.c Signed-off-by: Lu, Han <han.lu@intel.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
Diffstat (limited to 'include/sound/hda_register.h')
-rw-r--r--include/sound/hda_register.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h
index 2ae8812d7b1a..94dc6a9772e0 100644
--- a/include/sound/hda_register.h
+++ b/include/sound/hda_register.h
@@ -93,6 +93,9 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
#define AZX_REG_HSW_EM4 0x100c
#define AZX_REG_HSW_EM5 0x1010
+/* Skylake/Broxton display HD-A controller Extended Mode registers */
+#define AZX_REG_SKL_EM4L 0x1040
+
/* PCI space */
#define AZX_PCIREG_TCSEL 0x44