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| author | 2025-06-09 16:57:06 -0500 | |
|---|---|---|
| committer | 2025-07-03 16:29:45 +0200 | |
| commit | 0d495db1b9bd4c3eefc201c5e1c92fd1b96ecf2e (patch) | |
| tree | ccd664e2bea839cab5e6c4a833900b330b29a3f6 /include/uapi/linux/android/ssh:/git@git.zx2c4.com | |
| parent | arm64: dts: lg: Add missing PL011 "uartclk" (diff) | |
arm64: dts: cavium: thunder2: Add missing PL011 "uartclk"
The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
Thunder2 SoC is missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250609215706.3009692-2-robh@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'include/uapi/linux/android/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions
