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authorDillon Varone <Dillon.Varone@amd.com>2025-08-14 12:01:15 -0400
committerAlex Deucher <alexander.deucher@amd.com>2025-08-27 13:57:50 -0400
commit6b34e7ed4ba583ee77032a4c850ff97ba16ad870 (patch)
tree91ee1808d01fbd8381f8a31439188d4bfafea057 /include/uapi/linux/android/ssh:/git@git.zx2c4.com
parentdrm/amd/display: Array offset used before range check (diff)
drm/amd/display: Consider sink max slice width limitation for dsc
[WHY&HOW] The sink max slice width limitation should be considered for DSC, but was removed in "refactor DSC cap calculations". This patch adds it back and takes the valid minimum between the sink and source. Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/uapi/linux/android/ssh:/git@git.zx2c4.com')
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