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| author |   Alexey Charkov <alchark@gmail.com> | 2025-05-15 22:38:44 +0300 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2025-06-12 17:25:18 +0200 |
| commit | 6cd594ed969d5cfc7f97029f8ca0d240637ebb8d (patch) | |
| tree | e8c56d83a5a4c5f93f6ce7386f8ccb5868441968 /include/uapi/linux/android/ssh:/git@git.zx2c4.com | |
| parent | ARM: dts: vt8500: Fix the unit address of the VT8500 LCD controller (diff) | |
ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950
WonderMedia WM8850/WM8950 uses an ARM PL310 cache controller for its
L2 cache, add it.
The parameters have been deduced from vendor's U-boot environment
variables, which the downstream code uses to initialize the
controller. They set the following register values:
aux = 0x3e440000
prefetch_ctrl = 0x70000007
Their initialization code also unconditionally sets the flags
L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN, so encode those too
Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20250515-wmt-dts-updates-v2-5-246937484cc8@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'include/uapi/linux/android/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions