diff options
| author |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2025-02-10 21:44:50 +0200 |
|---|---|---|
| committer | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2025-02-11 16:25:41 +0200 |
| commit | 6edf3152bd4c2bc58e3705872642e282d8b3eeb9 (patch) | |
| tree | 14399146e39090523b80e6263ccf4aceb5d711d6 /include/uapi/linux/android/ssh:/git@git.zx2c4.com | |
| parent | MAINTAINERS: Add pin control and GPIO to the Intel MID record (diff) | |
pwm: lpss: Clarify the bypass member semantics in struct pwm_lpss_boardinfo
Instead of an odd comment, cite the documentation, which says more clearly
what's going on with the programming flow on some of the Intel SoCs.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Diffstat (limited to 'include/uapi/linux/android/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions