diff options
| author |   Leo Li <sunpeng.li@amd.com> | 2025-09-12 11:01:50 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2025-09-23 10:33:37 -0400 |
| commit | d43cc4ea1f9d720ab4bf06806f79260bfe981508 (patch) | |
| tree | 8c289b794cec2324d8d320b89538b059bc91bb7d /include/uapi/linux/android/ssh:/git@git.zx2c4.com | |
| parent | drm/amd/display: Revert "correct sw cache timing to ensure dispclk ramping" (diff) | |
drm/amd/display: Init DCN35 clocks from pre-os HW values
[Why]
We did not initialize dc clocks with boot-time hw values during init.
This lead to incorrect clock values in dc, causing `dcn35_update_clocks`
to make incorrect updates.
[How]
Correctly initialize DC with pre-os clk values from HW.
s/dump/save/ as that accurately reflects the purpose of the functions.
Fixes: 8774029f76b9 ("drm/amd/display: Add DCN35 CLK_MGR")
Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'include/uapi/linux/android/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions