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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2024-12-13 12:35:41 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-01-07 17:00:55 +0100 |
| commit | bb6a9aaf670735d6583c76073ec41190f5404dc5 (patch) | |
| tree | 6022c5340d86cf4597e388f45f7ae4c0d5a599ad /include/uapi/linux/byteorder/ssh:/git@git.zx2c4.com | |
| parent | Merge tag 'renesas-r9a09g047-dt-binding-defs-tag1' into renesas-clk-for-v6.14 (diff) | |
clk: renesas: rzv2h: Add support for RZ/G3E SoC
The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with
more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1
are present only on the RZ/G3E SoC.
Add minimal clock and reset entries required to boot the Renesas RZ/G3E
SMARC EVK and binds it with the RZ/V2H CPG core driver.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241213123550.289193-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'include/uapi/linux/byteorder/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions