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| author |   Matt Roper <matthew.d.roper@intel.com> | 2025-07-01 13:13:26 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2025-07-02 16:08:54 -0700 |
| commit | bd6a4b978584cb633be0d5cdfbf79803fd31da07 (patch) | |
| tree | 3aa47216e31519118d677aa391d085e2ce5e811c /include/uapi/linux/byteorder/ssh:/git@git.zx2c4.com | |
| parent | drm/xe/tests/pci: Ensure all platforms have a valid GT/tile count (diff) | |
drm/xe: Assign GT IDs properly on multi-tile + multi-GT platforms
Although "multi-tile" and "multiple GTs per tile" are mutually-exclusive
characteristics on all of our platforms today, this may not always be
true. Assign GT IDs according to xe->info.max_gt_per_tile in a way that
should work even if future platforms have different configurations.
This patch should not change the behavior of current platforms; it only
future-proofs for potential future designs.
v2:
- Re-calculate gt_count if tile count gets reduced by MTCFG. (PVC CI)
Reviewed-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Link: https://lore.kernel.org/r/20250701201320.2514369-14-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Diffstat (limited to 'include/uapi/linux/byteorder/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions