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authorMathias Nyman <mathias.nyman@linux.intel.com>2018-04-19 19:05:51 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2018-04-22 16:11:19 +0200
commit013eedb8c56e55549c45df19ca56a029cc804028 (patch)
treed0372e789faebaa0cb33f25f4d1b64528e631e00 /include/uapi/linux/usb
parentusb: define HCD_USB32 speed option for hosts that support USB 3.2 dual-lane (diff)
downloadwireguard-linux-013eedb8c56e55549c45df19ca56a029cc804028.tar.xz
wireguard-linux-013eedb8c56e55549c45df19ca56a029cc804028.zip
USB: Add support to store lane count used by USB 3.2
USB 3.2 specification adds Dual-lane support, doubling the maximum SuperSpeedPlus data rate from 10Gbps to 20Gbps. Dual-lane takes into use a second set of rx and tx wires/pins in the Type-C cable and connector. Add "rx_lanes" and "tx_lanes" variables to struct usb_device to store the numer of lanes in use. Number of lanes can be read using the extended port status hub request that was introduced in USB 3.1. Extended port status rx and tx lane count are zero based, maximum lanes supported by non inter-chip (SSIC) USB 3.2 is 2 (dual lane) with rx and tx lane count symmetric. SSIC devices support asymmetric lanes up to 4 lanes per direction. If extended port status is not available then default to one lane. Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'include/uapi/linux/usb')
-rw-r--r--include/uapi/linux/usb/ch11.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/uapi/linux/usb/ch11.h b/include/uapi/linux/usb/ch11.h
index 29c120c88747..fb0cd24c392c 100644
--- a/include/uapi/linux/usb/ch11.h
+++ b/include/uapi/linux/usb/ch11.h
@@ -197,6 +197,11 @@ struct usb_port_status {
#define USB_EXT_PORT_STAT_RX_LANES 0x00000f00
#define USB_EXT_PORT_STAT_TX_LANES 0x0000f000
+#define USB_EXT_PORT_RX_LANES(p) \
+ (((p) & USB_EXT_PORT_STAT_RX_LANES) >> 8)
+#define USB_EXT_PORT_TX_LANES(p) \
+ (((p) & USB_EXT_PORT_STAT_TX_LANES) >> 12)
+
/*
* wHubCharacteristics (masks)
* See USB 2.0 spec Table 11-13, offset 3