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| author |   Thomas Gleixner <tglx@linutronix.de> | 2016-05-11 12:06:25 +0200 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2016-05-11 12:06:25 +0200 |
| commit | 0097852c302aca943a8b76f7f85e133af6e1701a (patch) | |
| tree | 8246d163344fbe26dca0691602ceeff2d6503733 /include | |
| parent | irqchip/alpine-msi: Don't use <asm-generic/msi.h> (diff) | |
| parent | irqchip/bcm2836: Use a more generic memory barrier call (diff) | |
| download | wireguard-linux-0097852c302aca943a8b76f7f85e133af6e1701a.tar.xz wireguard-linux-0097852c302aca943a8b76f7f85e133af6e1701a.zip | |
Merge tag 'irqchip-for-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core
Pull irqchip updates for Linux 4.7 from Marc Zyngier
- Layerscape SCFG MSI controller support
- LPC32xx interrupt controller support
- RPi irqchip support on arm64
- GICv2 cleanup
- GICv2 and GICv3 bug fixes
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index d5d798b35c1f..9e6fdd33bdb2 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -102,8 +102,6 @@ #define GICR_SYNCR 0x00C0 #define GICR_MOVLPIR 0x0100 #define GICR_MOVALLR 0x0110 -#define GICR_ISACTIVER GICD_ISACTIVER -#define GICR_ICACTIVER GICD_ICACTIVER #define GICR_IDREGS GICD_IDREGS #define GICR_PIDR2 GICD_PIDR2 |