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| author |   David S. Miller <davem@davemloft.net> | 2020-07-06 13:18:56 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2020-07-06 13:18:56 -0700 |
| commit | 1eafa7369f170ac7dbe06a3774e642084051d475 (patch) | |
| tree | 2cefdc21fe5215aeb3b9be1d199fbd251c775e18 /include | |
| parent | geneve: move all configuration under struct geneve_config (diff) | |
| parent | net: qede: fix BE vs CPU comparison (diff) | |
| download | wireguard-linux-1eafa7369f170ac7dbe06a3774e642084051d475.tar.xz wireguard-linux-1eafa7369f170ac7dbe06a3774e642084051d475.zip | |
Merge branch 'qed-warnings-cleanup'
Alexander Lobakin says:
====================
net: qed/qede: W=1 C=1 warnings cleanup
This set cleans qed/qede build log under W=1 C=1 with GCC 8 and
sparse 0.6.2. The only thing left is "context imbalance -- unexpected
unlock" in one of the source files, which will be issued later during
the refactoring cycles.
The biggest part is handling the endianness warnings. The current code
often just assumes that both host and device operate in LE, which is
obviously incorrect (despite the fact that it's true for x86 platforms),
and makes sparse {s,m}ad.
The rest of the series is mostly random non-functional fixes
here-and-there.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/qed/qed_if.h | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/include/linux/qed/qed_if.h b/include/linux/qed/qed_if.h index 5ca081cd2ed9..90e1060da02b 100644 --- a/include/linux/qed/qed_if.h +++ b/include/linux/qed/qed_if.h @@ -1403,16 +1403,15 @@ static inline void qed_sb_ack(struct qed_sb_info *sb_info, enum igu_int_cmd int_cmd, u8 upd_flg) { - struct igu_prod_cons_update igu_ack = { 0 }; + u32 igu_ack; - igu_ack.sb_id_and_flags = - ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | - (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | - (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | - (IGU_SEG_ACCESS_REG << - IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); + igu_ack = ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | + (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | + (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | + (IGU_SEG_ACCESS_REG << + IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); - DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags); + DIRECT_REG_WR(sb_info->igu_addr, igu_ack); /* Both segments (interrupts & acks) are written to same place address; * Need to guarantee all commands will be received (in-order) by HW. |