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authorAnup Patel <anup.patel@wdc.com>2020-08-17 18:12:49 +0530
committerPalmer Dabbelt <palmerdabbelt@google.com>2020-08-20 10:57:29 -0700
commit2ac6795fcc085e8d03649f1bbd0d70aaff612cad (patch)
treedfefdd222a88f7c4fae17de7affd5c954a42dd91 /include
parentRISC-V: Add mechanism to provide custom IPI operations (diff)
downloadwireguard-linux-2ac6795fcc085e8d03649f1bbd0d70aaff612cad.tar.xz
wireguard-linux-2ac6795fcc085e8d03649f1bbd0d70aaff612cad.zip
clocksource/drivers: Add CLINT timer driver
We add a separate CLINT timer driver for Linux RISC-V M-mode (i.e. RISC-V NoMMU kernel). The CLINT MMIO device provides three things: 1. 64bit free running counter register 2. 64bit per-CPU time compare registers 3. 32bit per-CPU inter-processor interrupt registers Unlike other timer devices, CLINT provides IPI registers along with timer registers. To use CLINT IPI registers, the CLINT timer driver provides IPI related callbacks to arch/riscv. Signed-off-by: Anup Patel <anup.patel@wdc.com> Tested-by: Emil Renner Berhing <kernel@esmil.dk> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/cpuhotplug.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index a2710e654b64..3215023d4852 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -132,6 +132,7 @@ enum cpuhp_state {
CPUHP_AP_MIPS_GIC_TIMER_STARTING,
CPUHP_AP_ARC_TIMER_STARTING,
CPUHP_AP_RISCV_TIMER_STARTING,
+ CPUHP_AP_CLINT_TIMER_STARTING,
CPUHP_AP_CSKY_TIMER_STARTING,
CPUHP_AP_HYPERV_TIMER_STARTING,
CPUHP_AP_KVM_STARTING,