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| author |   Graf Yang <graf.yang@analog.com> | 2009-07-10 11:34:51 +0000 |
|---|---|---|
| committer |   Mike Frysinger <vapier@gentoo.org> | 2009-07-16 01:52:51 -0400 |
| commit | 5bc6e3cfe6db5f33c60f042a9ba203431f334756 (patch) | |
| tree | ff171234a9d19171e955bc1d05279e38c4b39f97 /include | |
| parent | Blackfin: work around anomaly 05000189 (diff) | |
| download | wireguard-linux-5bc6e3cfe6db5f33c60f042a9ba203431f334756.tar.xz wireguard-linux-5bc6e3cfe6db5f33c60f042a9ba203431f334756.zip | |
Blackfin: add CPLB entries for Core B on-chip L1 SRAM regions
The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM
regions. Any code that attempted to use these would wrongly crash due to
a CPLB miss.
Signed-off-by: Graf Yang <graf.yang@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions