diff options
| author |   Tero Kristo <t-kristo@ti.com> | 2014-10-03 16:57:12 +0300 |
|---|---|---|
| committer |   Paul Walmsley <paul@pwsan.com> | 2014-11-13 09:26:25 -0700 |
| commit | 83501ff0a5032dfbd63ab1ca9d9d25b97ec49fb9 (patch) | |
| tree | 97c507d2043017e968449341c666fc05094c430d /include | |
| parent | ARM: OMAP3: clock: add new rate changing logic support for noncore DPLLs (diff) | |
| download | wireguard-linux-83501ff0a5032dfbd63ab1ca9d9d25b97ec49fb9.tar.xz wireguard-linux-83501ff0a5032dfbd63ab1ca9d9d25b97ec49fb9.zip | |
ARM: OMAP4: clock: add support for determine_rate for omap4 regm4xen DPLL
Similarly to OMAP3 noncore DPLL, the implementation of this DPLL clock
type is wrong. This patch adds basic functionality for determine_rate
for this clock type which will be taken into use in the patches following
later.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/clk/ti.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 6f9fb77ffdd5..abc702a73aca 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -270,6 +270,10 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, unsigned long target_rate, unsigned long *parent_rate); +long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *best_parent_rate, + struct clk **best_parent_clk); u8 omap2_init_dpll_parent(struct clk_hw *hw); unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate); long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate, |