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| author |   Stephen Boyd <sboyd@kernel.org> | 2019-04-19 13:11:39 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-04-19 13:11:39 -0700 |
| commit | 93737fe93ec6cd3ffe49f631ad854c36a3d78ac2 (patch) | |
| tree | e4f65c542420799e6cbce22297c5f05008b1ccdf /include | |
| parent | Linux 5.1-rc1 (diff) | |
| parent | clk: sunxi-ng: sun5i: Export the MBUS clock (diff) | |
| download | wireguard-linux-93737fe93ec6cd3ffe49f631ad854c36a3d78ac2.tar.xz wireguard-linux-93737fe93ec6cd3ffe49f631ad854c36a3d78ac2.zip | |
Merge tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner
Pull Allwinner clk driver updates from Maxime Ripard:
Our usual bunch of changes, this time, it's mainly:
- Export a new clock for the MBUS controller on the A13
- H6 fixes to support a finer clocking of the video and VPU engines
- Add some Kconfig options
- Some bit offset fixes
* tag 'sunxi-clk-for-5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: sun5i: Export the MBUS clock
clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk
clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate
clk: sunxi-ng: h6: Preset hdmi-cec clock parent
clk: sunxi: Add Kconfig options
clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
clk: sunxi-ng: Allow DE clock to set parent rate
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/sun5i-ccu.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h index 81f34d477aeb..2e6b9ddcc24e 100644 --- a/include/dt-bindings/clock/sun5i-ccu.h +++ b/include/dt-bindings/clock/sun5i-ccu.h @@ -100,7 +100,7 @@ #define CLK_AVS 96 #define CLK_HDMI 97 #define CLK_GPU 98 - +#define CLK_MBUS 99 #define CLK_IEP 100 #endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ |