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| author |   Robert Jarzmik <robert.jarzmik@free.fr> | 2014-07-30 22:51:01 +0200 |
|---|---|---|
| committer |   Mike Turquette <mturquette@linaro.org> | 2014-09-30 12:31:31 -0700 |
| commit | 108f303f0ed92549b061e08a18361ad4bd540b27 (patch) | |
| tree | d2351bf8d0f576d4ea0cc18ccf6b7a4376939331 /mm/backing-dev.c | |
| parent | clk: dts: document pxa clock binding (diff) | |
| download | wireguard-linux-108f303f0ed92549b061e08a18361ad4bd540b27.tar.xz wireguard-linux-108f303f0ed92549b061e08a18361ad4bd540b27.zip | |
arm: pxa: add clock pll selection bits
Add missing bits for CCCR and CCSR :
- CPLL and PPLL selection, either full speed or 13MHz
- CPSR masks
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'mm/backing-dev.c')
0 files changed, 0 insertions, 0 deletions