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| author |   Ricky WU <ricky_wu@realtek.com> | 2022-03-02 09:43:01 +0000 |
|---|---|---|
| committer |   Ulf Hansson <ulf.hansson@linaro.org> | 2022-03-02 11:38:28 +0100 |
| commit | 1f311c94aabdb419c28e3147bcc8ab89269f1a7e (patch) | |
| tree | bb08feb1704b2850d88faeccaa35bd8343bfa6c3 /mm/util.c | |
| parent | dt-bindings: mmc: renesas,sdhi: Document RZ/V2L SoC (diff) | |
| download | wireguard-linux-1f311c94aabdb419c28e3147bcc8ab89269f1a7e.tar.xz wireguard-linux-1f311c94aabdb419c28e3147bcc8ab89269f1a7e.zip | |
mmc: rtsx: add 74 Clocks in power on flow
SD spec definition:
"Host provides at least 74 Clocks before issuing first command"
After 1ms for the voltage stable then start issuing the Clock signals
if POWER STATE is
MMC_POWER_OFF to MMC_POWER_UP to issue Clock signal to card
MMC_POWER_UP to MMC_POWER_ON to stop issuing signal to card
Signed-off-by: Ricky Wu <ricky_wu@realtek.com>
Link: https://lore.kernel.org/r/1badf10aba764191a1a752edcbf90389@realtek.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'mm/util.c')
0 files changed, 0 insertions, 0 deletions