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| author |   Borislav Petkov <borislav.petkov@amd.com> | 2012-09-13 18:53:58 +0200 |
|---|---|---|
| committer |   Borislav Petkov <bp@alien8.de> | 2012-11-28 11:54:40 +0100 |
| commit | 16a528ee3975c860dc93fbfc718fe9aa25ed92bc (patch) | |
| tree | ea0d20d3544df6dfe2977634d1a4cc837f80b964 /mm | |
| parent | EDAC: Pass mci parent (diff) | |
| download | wireguard-linux-16a528ee3975c860dc93fbfc718fe9aa25ed92bc.tar.xz wireguard-linux-16a528ee3975c860dc93fbfc718fe9aa25ed92bc.zip | |
EDAC: Fix csrow size reported in sysfs
On csrow-based memory controllers, we combine the csrow size from both
channels and there's no need to do that again in csrow_size_show which
leads to double the size of a csrow.
Fix it.
Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
Diffstat (limited to 'mm')
0 files changed, 0 insertions, 0 deletions