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| author |   André Draszik <andre.draszik@linaro.org> | 2024-12-05 10:22:00 +0000 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2025-02-14 17:58:21 +0530 |
| commit | 8789b4296aa796f658a19cac7d27365012893de1 (patch) | |
| tree | 832b88e932b0a269bc34b3bfc962b08c48c9738d /rust/helpers/helpers.c | |
| parent | phy: freescale: fsl-samsung-hdmi: Limit PLL lock detection clock divider to valid range (diff) | |
| download | wireguard-linux-8789b4296aa796f658a19cac7d27365012893de1.tar.xz wireguard-linux-8789b4296aa796f658a19cac7d27365012893de1.zip | |
phy: exynos5-usbdrd: gs101: ensure power is gated to SS phy in phy_exit()
We currently don't gate the power to the SS phy in phy_exit().
Shuffle the code slightly to ensure the power is gated to the SS phy as
well.
Fixes: 32267c29bc7d ("phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)")
CC: stable@vger.kernel.org # 6.11+
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20241205-gs101-usb-phy-fix-v4-1-0278809fb810@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'rust/helpers/helpers.c')
0 files changed, 0 insertions, 0 deletions