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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2025-06-04 10:50:39 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-06-04 10:50:39 -0500 |
| commit | 20611193be984391b5ec80a372e7f8bbc7c5b07a (patch) | |
| tree | cdd2a305ff46f2c9216fac457c52e973726bb553 /rust/helpers/pci.c | |
| parent | Merge branch 'pci/controller/dwc-ep' (diff) | |
| parent | PCI: dwc: Make link training more robust by setting PORT_LOGIC_LINK_WIDTH to one lane (diff) | |
| download | wireguard-linux-20611193be984391b5ec80a372e7f8bbc7c5b07a.tar.xz wireguard-linux-20611193be984391b5ec80a372e7f8bbc7c5b07a.zip | |
Merge branch 'pci/controller/dwc'
- Set PORT_LOGIC_LINK_WIDTH to one lane to make initial link training more
robust; this will not affect the intended link width if all lanes are
functional (Wenbin Yao)
* pci/controller/dwc:
PCI: dwc: Make link training more robust by setting PORT_LOGIC_LINK_WIDTH to one lane
Diffstat (limited to 'rust/helpers/pci.c')
0 files changed, 0 insertions, 0 deletions