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| author |   Lu Baolu <baolu.lu@linux.intel.com> | 2023-11-22 11:26:03 +0800 |
|---|---|---|
| committer |   Joerg Roedel <jroedel@suse.de> | 2023-11-27 11:07:51 +0100 |
| commit | 0f5432a9b839847dcfe9fa369d72e3d646102ddf (patch) | |
| tree | cb0c12860a622c6794190d764a0edd5fe3adc5db /rust/kernel/ssh:/git@git.zx2c4.com/git: | |
| parent | iommu/vt-d: Support enforce_cache_coherency only for empty domains (diff) | |
iommu/vt-d: Omit devTLB invalidation requests when TES=0
The latest VT-d spec indicates that when remapping hardware is disabled
(TES=0 in Global Status Register), upstream ATS Invalidation Completion
requests are treated as UR (Unsupported Request).
Consequently, the spec recommends in section 4.3 Handling of Device-TLB
Invalidations that software refrain from submitting any Device-TLB
invalidation requests when address remapping hardware is disabled.
Verify address remapping hardware is enabled prior to submitting Device-
TLB invalidation requests.
Fixes: 792fb43ce2c9 ("iommu/vt-d: Enable Intel IOMMU scalable mode by default")
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Link: https://lore.kernel.org/r/20231114011036.70142-2-baolu.lu@linux.intel.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Diffstat (limited to 'rust/kernel/ssh:/git@git.zx2c4.com/git:')
0 files changed, 0 insertions, 0 deletions