diff options
| author |   Emil Renner Berthing <emil.renner.berthing@canonical.com> | 2023-11-30 16:19:28 +0100 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2023-12-13 15:50:23 +0000 |
| commit | d4b95c445cab0fb583eed7caafbc1b734f6a3a59 (patch) | |
| tree | be378d740f95deca4270369291edb73d6fe1fc2c /rust/kernel/ssh:/git@git.zx2c4.com/git: | |
| parent | riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs (diff) | |
riscv: dts: starfive: Add JH7100 cache controller
The StarFive JH7100 SoC also features the SiFive L2 cache controller,
so add the device tree nodes for it.
Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'rust/kernel/ssh:/git@git.zx2c4.com/git:')
0 files changed, 0 insertions, 0 deletions