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| author |   Vamshi Gajjela <vamshigajjela@google.com> | 2023-12-31 23:59:51 +0530 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-01-04 16:21:43 +0100 |
| commit | d8a02844791360ed156ce5935bc50754ea22e299 (patch) | |
| tree | 3ee39812e7b95fe01e90b75babcb0843303e4749 /rust/kernel/ssh:/git@git.zx2c4.com/git: | |
| parent | serial: imx: Ensure that imx_uart_rs485_config() is called with enabled clock (diff) | |
serial: 8250_dw: Do not bailout on UCV read returning zero
Designware UART has optional feature FIFO_MODE to implement FIFO.
Encoding FIFO capabilities through Component Parameter Register CPR is
optional and it can be enabled using parameter UART_ADD_ENCODED_PARAMS.
Driver can exercise fifo capabilities by decoding CPR if implemented
or from cpr_val provided from the dw8250_platform_data otherwise.
dw8250_setup_port() checks for CPR or cpr_val to determine FIFO size
only when Component Version (UCV) is non-zero. Bailing out early on UCV
read returning zero will leave fifosize as zero and !UART_CAP_FIFO,
hence prevent early return and continue to process CPR or cpr_val for
the driver to utilize FIFO.
Non-zero UCV implies ADDITIONAL_FEATURES=1, preventing early return
will not be an overhead here.
Signed-off-by: Vamshi Gajjela <vamshigajjela@google.com>
Link: https://lore.kernel.org/r/20231231182951.877805-1-vamshigajjela@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'rust/kernel/ssh:/git@git.zx2c4.com/git:')
0 files changed, 0 insertions, 0 deletions