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| author |   Andrew Jones <ajones@ventanamicro.com> | 2023-12-13 18:09:56 +0100 |
|---|---|---|
| committer |   Anup Patel <anup@brainfault.org> | 2023-12-29 12:31:47 +0530 |
| commit | 6ccf119a4cc886678099a3526f37db98b67024d7 (patch) | |
| tree | 3775c08b15df38cc0a51bfd8e8d6718487b238d4 /rust/kernel/ssh:/git@git.zx2c4.com | |
| parent | RISC-V: KVM: Make SBI uapi consistent with ISA uapi (diff) | |
KVM: riscv: selftests: Add RISCV_SBI_EXT_REG
While adding RISCV_SBI_EXT_REG(), acknowledge that some registers
have subtypes and extend __kvm_reg_id() to take a subtype field.
Then, update all macros to set the new field appropriately. The
general CSR macro gets renamed to include "GENERAL", but the other
macros, like the new RISCV_SBI_EXT_REG, just use the SINGLE subtype.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'rust/kernel/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions