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author | 2025-02-14 16:14:27 -0800 | |
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committer | 2025-03-05 04:34:12 +0200 | |
commit | 2ea34682263b90566130d70a20bc742ed8de2e3f (patch) | |
tree | d56ea104761b747d27810f765bf60c4d56816c9a /rust/pin-init/internal/src | |
parent | drm/msm/dpu: switch RM to use crtc_id rather than enc_id for allocation (diff) | |
download | wireguard-linux-2ea34682263b90566130d70a20bc742ed8de2e3f.tar.xz wireguard-linux-2ea34682263b90566130d70a20bc742ed8de2e3f.zip |
drm/msm/dpu: Add CWB to msm_display_topology
Currently, the topology is calculated based on the assumption that the
user cannot request real-time and writeback simultaneously. For example,
the number of LMs and CTLs are currently based off the number of phys
encoders under the assumption there will be at least 1 LM/CTL per phys
encoder.
This will not hold true for concurrent writeback as both phys encoders
(1 real-time and 1 writeback) must be driven by 1 LM/CTL when concurrent
writeback is enabled.
To account for this, add a cwb_enabled flag and only adjust the number of
CTL/LMs needed by a given topology based on the number of phys encoders
only if CWB is not enabled.
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/637486/
Link: https://lore.kernel.org/r/20250214-concurrent-wb-v6-4-a44c293cf422@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'rust/pin-init/internal/src')
0 files changed, 0 insertions, 0 deletions