diff options
| author |   Thierry Bultel <thierry.bultel.yh@bp.renesas.com> | 2025-05-15 16:18:17 +0200 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-05-26 13:51:00 +0200 |
| commit | 4e591b890afa0cbc3479f3b88fa7dc1d28972761 (patch) | |
| tree | caeeb8f02494f52164909397d10cb08152876d6d /rust/pin-init/internal/src | |
| parent | dt-bindings: soc: renesas: Add Renesas RZ/T2H (R9A09G077) SoC (diff) | |
| download | wireguard-linux-4e591b890afa0cbc3479f3b88fa7dc1d28972761.tar.xz wireguard-linux-4e591b890afa0cbc3479f3b88fa7dc1d28972761.zip | |
dt-bindings: clock: renesas,cpg-mssr: Document RZ/T2H support
Document RZ/T2H (a.k.a. r9a09g077) cpg-mssr (Clock Pulse Generator)
binding.
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250515141828.43444-3-thierry.bultel.yh@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'rust/pin-init/internal/src')
0 files changed, 0 insertions, 0 deletions