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| author |   Jesse Zhang <jesse.zhang@amd.com> | 2025-06-25 15:29:45 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2025-07-16 16:17:35 -0400 |
| commit | 78d0a27ae0e2e70b22895f4b388cc0ab88e3c6ca (patch) | |
| tree | 781b64d869e4eca92533245847798b58fe60cb1e /rust/pin-init/internal/src | |
| parent | drm/amd/amdgpu: Add helper functions for isp buffers (diff) | |
| download | wireguard-linux-78d0a27ae0e2e70b22895f4b388cc0ab88e3c6ca.tar.xz wireguard-linux-78d0a27ae0e2e70b22895f4b388cc0ab88e3c6ca.zip | |
drm/amdgpu: Add user queue instance count in HW IP info
This change exposes the number of available user queue instances
for each hardware IP type (GFX, COMPUTE, SDMA) through the
drm_amdgpu_info_hw_ip interface.
Key changes:
1. Added userq_num_instance field to drm_amdgpu_info_hw_ip structure
2. Implemented counting of available HQD slots using:
- mes.gfx_hqd_mask for GFX queues
- mes.compute_hqd_mask for COMPUTE queues
- mes.sdma_hqd_mask for SDMA queues
3. Only counts available instances when user queues are enabled
(!disable_uq)
v2: using the adev->mes.gfx_hqd_mask[]/compute_hqd_mask[]/sdma_hqd_mask[] masks
to determine the number of queue slots available for each engine type (Alex)
v3: rename userq_num_instance to userq_num_hqds (Alex)
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'rust/pin-init/internal/src')
0 files changed, 0 insertions, 0 deletions