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| author |   Gabor Juhos <j4g8y7@gmail.com> | 2025-07-23 10:06:43 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2025-07-23 13:04:03 +0100 |
| commit | f820034864dd463cdcd2bebe7940f2eca0eb4223 (patch) | |
| tree | ace4cb6af172576a43528394b528c064e93906d4 /rust/pin-init/internal/src | |
| parent | spi: Add check for 8-bit transfer with 8 IO mode support (diff) | |
| download | wireguard-linux-f820034864dd463cdcd2bebe7940f2eca0eb4223.tar.xz wireguard-linux-f820034864dd463cdcd2bebe7940f2eca0eb4223.zip | |
spi: spi-qpic-snand: don't hardcode ECC steps
NAND devices with different page sizes requires different number
of ECC steps, yet the qcom_spi_ecc_init_ctx_pipelined() function
sets 4 steps in 'ecc_cfg' unconditionally.
The correct number of the steps is calculated earlier in the
function already, so use that instead of the hardcoded value.
Fixes: 7304d1909080 ("spi: spi-qpic: add driver for QCOM SPI NAND flash Interface")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://patch.msgid.link/20250723-qpic-snand-fix-steps-v1-1-d800695dde4c@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'rust/pin-init/internal/src')
0 files changed, 0 insertions, 0 deletions