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| author |   Yao Zi <ziyao@disroot.org> | 2025-09-19 14:26:46 +0000 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2025-09-21 12:48:49 -0700 |
| commit | 158ddb87b13e6642dadaa16e3c4e9f5814825685 (patch) | |
| tree | 401279f78059640409a490536ee60796f1bb7a4e /scripts/basic/git:/ssh:/git@git.zx2c4.com | |
| parent | clk: loongson2: Allow zero divisors for dividers (diff) | |
| download | wireguard-linux-158ddb87b13e6642dadaa16e3c4e9f5814825685.tar.xz wireguard-linux-158ddb87b13e6642dadaa16e3c4e9f5814825685.zip | |
clk: loongson2: Avoid hardcoding firmware name of the reference clock
Loongson-2K0300 requires a reference clock with a frequency different
from previous SoCs (120MHz v.s. 100MHz), thus hardcoding the firmware
name of the reference clock as ref_100m isn't a good idea.
This patch retrives the clock name of the reference clock dynamically
during probe, avoiding the hardcoded pdata structure and preparing for
support of future SoCs.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'scripts/basic/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions