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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-09-04 16:55:07 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-09-11 20:23:15 +0200 |
| commit | 2cfff084f03005079f900fe6d0a031f7c508e881 (patch) | |
| tree | 02dfdb335a5ec14e7dd20f9c3e8ca464f8bcfbf1 /scripts/basic/git:/ssh:/git@git.zx2c4.com | |
| parent | clk: renesas: r9a09g057: Add clock and reset entries for I3C (diff) | |
| download | wireguard-linux-2cfff084f03005079f900fe6d0a031f7c508e881.tar.xz wireguard-linux-2cfff084f03005079f900fe6d0a031f7c508e881.zip | |
clk: renesas: r9a09g056: Add clock and reset entries for I3C
Add module clock entries for the I3C controller on the RZ/V2N
(R9A09G056) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250904155507.245744-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/basic/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions