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| author |   E Shattow <e@freeshell.de> | 2025-01-02 10:37:37 -0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2025-02-18 16:32:25 +0000 |
| commit | 38818f7c9c179351334b1faffc4d40bd28cc9c72 (patch) | |
| tree | 4890f5088bd96558b719e48f45a3c90248090dc0 /scripts/basic/git:/ssh:/git@git.zx2c4.com | |
| parent | riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers (diff) | |
| download | wireguard-linux-38818f7c9c179351334b1faffc4d40bd28cc9c72.tar.xz wireguard-linux-38818f7c9c179351334b1faffc4d40bd28cc9c72.zip | |
riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port
One of four USB-A ports on the Pine64 Star64 is USB 3.0 which requires to
disable PCIE0 and change the mode of PCIE0 PHY to USB3.0 operation. The
remaining three USB-A ports are USB 2.0 with the USB0 PHY and do not
conflict with any of PCIE0 or PCIE1. PCIE1 (1-lane) routes to a PCIe X4
connector.
Signed-off-by: E Shattow <e@freeshell.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'scripts/basic/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions