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| author |   Wolfram Sang <wsa+renesas@sang-engineering.com> | 2024-11-22 11:14:48 +0100 |
|---|---|---|
| committer |   Alexandre Belloni <alexandre.belloni@bootlin.com> | 2024-11-25 23:32:50 +0100 |
| commit | 3ed345c948ef6ccd0f5dc85c5b6731593b4591f7 (patch) | |
| tree | 7b596d3b43e5ba621b1725091694f0902d1de420 /scripts/basic/git:/ssh:/git@git.zx2c4.com | |
| parent | rtc: rzn1: drop superfluous wday calculation (diff) | |
| download | wireguard-linux-3ed345c948ef6ccd0f5dc85c5b6731593b4591f7.tar.xz wireguard-linux-3ed345c948ef6ccd0f5dc85c5b6731593b4591f7.zip | |
rtc: rzn1: reduce register access
This RTC has special 32bit registers which return multiple of the same
8bit registers at once. Use these to minimize register access. Also, do
the to/from BCD conversions right away, so 'tm' always contains values
as described in time.h.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20241122101448.4374-3-wsa+renesas@sang-engineering.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Diffstat (limited to 'scripts/basic/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions