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| author |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2025-07-24 10:38:43 +0200 |
|---|---|---|
| committer |   Rob Herring (Arm) <robh@kernel.org> | 2025-09-26 14:50:44 -0500 |
| commit | 8d200dff1e8e0cb521dd48ba1d5424be400cd9bc (patch) | |
| tree | a18ca685175af06356609cc924f437c7e58995c6 /scripts/basic/git:/ssh:/git@git.zx2c4.com | |
| parent | dt-bindings: timer: mediatek: Add compatible for MT6795 GP Timer (diff) | |
| download | wireguard-linux-8d200dff1e8e0cb521dd48ba1d5424be400cd9bc.tar.xz wireguard-linux-8d200dff1e8e0cb521dd48ba1d5424be400cd9bc.zip | |
dt-bindings: pinctrl: mediatek,mt7622-pinctrl: Add missing pwm_ch7_2
The MT7622 SoC has a PWM channel 7-2 group for the pwm7 IP: add
the missing pwm_ch7_2 group.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Diffstat (limited to 'scripts/basic/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions