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| author |   Ryan Wanner <Ryan.Wanner@microchip.com> | 2025-09-08 13:07:17 -0700 |
|---|---|---|
| committer |   Nicolas Ferre <nicolas.ferre@microchip.com> | 2025-09-17 19:15:32 +0200 |
| commit | e0237f5635727d64635ec6665e1de9f4cacce35c (patch) | |
| tree | 463a35def2787c6d86052c60a5147b9f65c34118 /scripts/basic/git:/ssh:/git@git.zx2c4.com | |
| parent | clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register (diff) | |
| download | wireguard-linux-e0237f5635727d64635ec6665e1de9f4cacce35c.tar.xz wireguard-linux-e0237f5635727d64635ec6665e1de9f4cacce35c.zip | |
clk: at91: clk-master: Add check for divide by 3
A potential divider for the master clock is div/3. The register
configuration for div/3 is MASTER_PRES_MAX. The current bit shifting
method does not work for this case. Checking for MASTER_PRES_MAX will
ensure the correct decimal value is stored in the system.
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Diffstat (limited to 'scripts/basic/git:/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions