diff options
| author |   Laurent Pinchart <laurent.pinchart@ideasonboard.com> | 2025-06-16 04:11:15 +0300 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2025-09-11 10:37:32 +0800 |
| commit | 8647d8a7709d7619cb26467957b846989c4459d0 (patch) | |
| tree | d1707c0c1aaee722c24660c5d0f60b8814b3a695 /scripts/basic/git: | |
| parent | arm64: dts: imx95: add fsl,phy-tx-vref-tune-percent tuning properties for USB3 PHY (diff) | |
arm64: dts: imx8mp: Add pclk clock and second power domain for the ISP
The ISP HDR stitching registers are clocked by the pixel clock, which is
gated by the MIPI_CSI2 power domain. Attempting to access those
registers with the clock off locks up the system. Fix this by adding the
pclk clock and the MIPI_CSI2 secondary power domain.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'scripts/basic/git:')
0 files changed, 0 insertions, 0 deletions