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| author |   Mika Westerberg <mika.westerberg@linux.intel.com> | 2018-09-24 17:32:11 +0300 |
|---|---|---|
| committer |   Linus Walleij <linus.walleij@linaro.org> | 2018-09-25 12:48:15 +0200 |
| commit | e50d95e2ad1266f8d3fcdf0724f03dbdffd400aa (patch) | |
| tree | df2ba3b4c9b71a6ef48c889510340a118fa46497 /scripts/gdb/linux/lists.py | |
| parent | pinctrl/amd: poll InterruptEnable bits in amd_gpio_irq_set_type (diff) | |
| download | wireguard-linux-e50d95e2ad1266f8d3fcdf0724f03dbdffd400aa.tar.xz wireguard-linux-e50d95e2ad1266f8d3fcdf0724f03dbdffd400aa.zip | |
pinctrl: cannonlake: Fix HOSTSW_OWN register offset of H variant
It turns out the HOSTSW_OWN register offset is different between LP and
H variants. The latter should use 0xc0 instead so fix that.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=199911
Fixes: a663ccf0fea1 ("pinctrl: intel: Add Intel Cannon Lake PCH-H pin controller support")
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'scripts/gdb/linux/lists.py')
0 files changed, 0 insertions, 0 deletions