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| author |   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2024-06-24 00:16:17 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-06-27 18:17:00 +0200 |
| commit | 1f5ed3ae020a0624c9f51ed9720f8279bb0cae60 (patch) | |
| tree | 5a67f13d4927b39814d7907f3898407762b7be7a /scripts/gdb/linux/modules.py | |
| parent | clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP (diff) | |
| download | wireguard-linux-1f5ed3ae020a0624c9f51ed9720f8279bb0cae60.tar.xz wireguard-linux-1f5ed3ae020a0624c9f51ed9720f8279bb0cae60.zip | |
clk: renesas: r8a779h0: Add Audio clocks
Add module clocks for the Audio (SSI/SSIU) blocks on the Renesas R-Car
V4M (R8A779H0) SoC.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/87h6djkxf2.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions