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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-11-06 08:52:27 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-11-06 08:52:27 +0100 |
| commit | 2978fdc22cd32733336ec821e7265518a02136e8 (patch) | |
| tree | fed01e92c01e72f61f49804d1c45e85d772a321d /scripts/gdb/linux/modules.py | |
| parent | clk: Add devm_clk_hw_register_gate_parent_hw() (diff) | |
| parent | dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB (diff) | |
| download | wireguard-linux-2978fdc22cd32733336ec821e7265518a02136e8.tar.xz wireguard-linux-2978fdc22cd32733336ec821e7265518a02136e8.zip | |
Merge tag 'renesas-r9a08g045-dt-binding-defs-tag3' into renesas-clk-for-v6.13
Renesas RZ/G3S DT Binding Definitions
VBATTB clock definitions for the Renesas RZ/G3S (R9A08G045) SoC, shared
by driver and DT source files.
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions