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| author |   Gabor Juhos <j4g8y7@gmail.com> | 2024-05-08 22:34:14 +0200 |
|---|---|---|
| committer |   Bjorn Andersson <andersson@kernel.org> | 2024-05-28 16:31:13 -0500 |
| commit | 5a33a64524e6381c399e5e42571d9363ffc0bed4 (patch) | |
| tree | 8b87bc2c71a57286182b6450b496c918839ad1b6 /scripts/gdb/linux/modules.py | |
| parent | clk: qcom: gcc-sm6350: Fix gpll6* & gpll7 parents (diff) | |
| download | wireguard-linux-5a33a64524e6381c399e5e42571d9363ffc0bed4.tar.xz wireguard-linux-5a33a64524e6381c399e5e42571d9363ffc0bed4.zip | |
clk: qcom: clk-alpha-pll: set ALPHA_EN bit for Stromer Plus PLLs
The clk_alpha_pll_stromer_plus_set_rate() function does not
sets the ALPHA_EN bit in the USER_CTL register, so setting
rates which requires using alpha mode works only if the bit
gets set already prior calling the function.
Extend the function to set the ALPHA_EN bit in order to allow
using fractional rates regardless whether the bit gets set
previously or not.
Fixes: 84da48921a97 ("clk: qcom: clk-alpha-pll: introduce stromer plus ops")
Signed-off-by: Gabor Juhos <j4g8y7@gmail.com>
Link: https://lore.kernel.org/r/20240508-stromer-plus-alpha-en-v1-1-6639ce01ca5b@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions