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| author |   Stephen Boyd <sboyd@codeaurora.org> | 2015-01-29 15:38:11 -0800 |
|---|---|---|
| committer |   Michael Turquette <mturquette@linaro.org> | 2015-02-25 12:08:38 -0800 |
| commit | 7dd47b8ef54c301ecde58cecf2f3e29ff3f48d4a (patch) | |
| tree | 7853b29ec1f180878d1f788edc65846b9d03839f /scripts/gdb/linux/modules.py | |
| parent | clk: ti: Fix FAPLL parent enable bit handling (diff) | |
| download | wireguard-linux-7dd47b8ef54c301ecde58cecf2f3e29ff3f48d4a.tar.xz wireguard-linux-7dd47b8ef54c301ecde58cecf2f3e29ff3f48d4a.zip | |
clk: qcom: Fix slimbus n and m val offsets
These shifts were copy/pasted from the pcm which is a different
size RCG. Use the correct offsets so that slimbus rates are
correct.
Fixes: b82875ee07e5 "clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions