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| author |   Sagi Grimberg <sagig@mellanox.com> | 2015-04-14 18:08:23 +0300 |
|---|---|---|
| committer |   Doug Ledford <dledford@redhat.com> | 2015-04-15 16:07:13 -0400 |
| commit | 8b95aa2c1bf8c936e5b0e9096b180a3e4f5327ff (patch) | |
| tree | 29737d4a93d2fe406b9f3ad2e3a5507a8899d5d7 /scripts/gdb/linux/modules.py | |
| parent | IB/iser: Move PI context alloc/free to routines (diff) | |
| download | wireguard-linux-8b95aa2c1bf8c936e5b0e9096b180a3e4f5327ff.tar.xz wireguard-linux-8b95aa2c1bf8c936e5b0e9096b180a3e4f5327ff.zip | |
IB/iser: Make fastreg pool cache friendly
Memory regions are resources that are saved
in the device caches. Increase the probability for
a cache hit by adding the MRU descriptor to pool
head.
Signed-off-by: Sagi Grimberg <sagig@mellanox.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions