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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2024-09-18 14:59:57 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-10-07 10:32:56 +0200 |
| commit | 8cce33aed0b6383e91bb9d26dae11b1293101381 (patch) | |
| tree | af2e04c749289acf305d227ea2eb1d526393e545 /scripts/gdb/linux/modules.py | |
| parent | clk: renesas: Remove duplicate and trailing empty lines (diff) | |
| download | wireguard-linux-8cce33aed0b6383e91bb9d26dae11b1293101381.tar.xz wireguard-linux-8cce33aed0b6383e91bb9d26dae11b1293101381.zip | |
clk: renesas: r9a09g057: Add CA55 core clocks
Add CA55 core clocks which are derived from PLLCA55.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240918135957.290101-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions