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| author |   Dave Airlie <airlied@redhat.com> | 2015-02-24 11:08:47 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2015-02-24 11:08:47 +1000 |
| commit | 8ee351625e9b784fa412ded8b15957a6d5e16bd3 (patch) | |
| tree | fc6b20dc05d0317cd62fe1eae13c2f6da9ccfeca /scripts/gdb/linux/modules.py | |
| parent | drm: Fix deadlock due to getconnector locking changes (diff) | |
| parent | drm/tegra: dc: Move more code into ->init() (diff) | |
| download | wireguard-linux-8ee351625e9b784fa412ded8b15957a6d5e16bd3.tar.xz wireguard-linux-8ee351625e9b784fa412ded8b15957a6d5e16bd3.zip | |
Merge tag 'drm/tegra/for-3.20-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux into drm-fixes
drm/tegra: Fixes for v3.20-rc1
This fixes a bit of fallout that was caused by the atomic modesetting
driver conversion and some last-minute changes in the DRM atomic core.
It also fixes a bug exposed by recent changes in the clock framework
which results in non-working HDMI.
* tag 'drm/tegra/for-3.20-rc1-fixes' of git://anongit.freedesktop.org/tegra/linux:
drm/tegra: dc: Move more code into ->init()
drm/tegra: dc: Wire up CRTC parent of atomic state
drm/tegra: dc: Reset state's active_changed field
drm/tegra: hdmi: Explicitly set clock rate
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions