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| author |   Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> | 2024-10-23 12:01:34 +0300 |
|---|---|---|
| committer |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-10-26 13:58:33 +0200 |
| commit | a81dca057273c32b8554b3bc562480d4b3816155 (patch) | |
| tree | b4d5c35bb53cb363ead8103615ee72f404d5f4d8 /scripts/gdb/linux/modules.py | |
| parent | dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions (diff) | |
| download | wireguard-linux-a81dca057273c32b8554b3bc562480d4b3816155.tar.xz wireguard-linux-a81dca057273c32b8554b3bc562480d4b3816155.zip | |
dt-bindings: clock: samsung: Add Exynos8895 SoC
Provide dt-schema documentation for Samsung Exynos8895 SoC clock
controller CMU blocks:
- CMU_FSYS0/1
- CMU_PERIC0/1
- CMU_PERIS
- CMU_TOP
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Link: https://lore.kernel.org/r/20241023090136.537395-2-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions