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| author |   Richard Zhu <hongxing.zhu@nxp.com> | 2024-10-15 15:34:04 +0800 |
|---|---|---|
| committer |   Abel Vesa <abel.vesa@linaro.org> | 2024-10-22 17:21:13 +0300 |
| commit | cf295252f0d88410d5793fa6db56a7192a65d66f (patch) | |
| tree | 55a943a579af9234f8aa97ed18a1837b6dd5f9cb /scripts/gdb/linux/modules.py | |
| parent | dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL (diff) | |
| download | wireguard-linux-cf295252f0d88410d5793fa6db56a7192a65d66f.tar.xz wireguard-linux-cf295252f0d88410d5793fa6db56a7192a65d66f.zip | |
clk: imx95-blk-ctl: Add one clock gate for HSIO block
CREF_EN (Bit6) of LFAST_IO_REG control i.MX95 PCIe REF clock out
enable/disable.
Add compatible string "nxp,imx95-hsio-blk-ctl" to support PCIe REF clock
out gate.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/1728977644-8207-3-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions