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| author |   Will Deacon <will.deacon@arm.com> | 2015-03-06 11:54:10 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-03-24 15:09:47 +0000 |
| commit | d5efd9cc9cf2e422d064c912c7d5d985f52c1b2c (patch) | |
| tree | ec4a29ce1df9016b48597888d55e925f3bdf4ac5 /scripts/gdb/linux/modules.py | |
| parent | dt: pmu: extend ARM PMU binding to allow for explicit interrupt affinity (diff) | |
| download | wireguard-linux-d5efd9cc9cf2e422d064c912c7d5d985f52c1b2c.tar.xz wireguard-linux-d5efd9cc9cf2e422d064c912c7d5d985f52c1b2c.zip | |
arm64: pmu: add support for interrupt-affinity property
Historically, the PMU devicetree bindings have expected SPIs to be
listed in order of *logical* CPU number. This is problematic for
bootloaders, especially when the boot CPU (logical ID 0) isn't listed
first in the devicetree.
This patch adds a new optional property, interrupt-affinity, to the
PMU node which allows the interrupt affinity to be described using
a list of phandled to CPU nodes, with each entry in the list
corresponding to the SPI at the same index in the interrupts property.
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions